j.BECOMING
JENSEN
繁中 ↗
FIELD NOTES / 02 · 1963—2025

No chip
works alone.

A guided map from an architecture decision to a deployed service. Choose a stage, then meet the collaborators around it.

BECOMING JENSENAN INDUSTRIAL ATLAS
01
THE PROCESS

Architecture & design

Define the operations a processor should accelerate. Hardware architects and software teams work together: a useful chip needs a usable programming model.

INPUT
Workloads, algorithms, IP
OUTPUT
A verified chip design
Arm · Neoverse and Grace · 2022 ↗
02
THE PROCESS

Wafer fabrication

Repeated deposition, patterning and etching build electronic circuits on a wafer. The foundry turns a design into physical silicon.

INPUT
Design files and process technology
OUTPUT
Many dies on one wafer
NVIDIA · Blackwell announcement · 2024-03-18 ↗
03
THE PROCESS

High-bandwidth memory

Compute needs a steady stream of data. Stacked HBM places substantial memory bandwidth close to the accelerator package.

INPUT
Memory dies and stacking
OUTPUT
Qualified HBM components
Micron · HBM3E / H200 · 2024-02-26 ↗
04
THE PROCESS

Packaging & test

Chips and memory must be connected, protected and tested. Advanced packaging is an integration discipline, not simply a protective box.

INPUT
Known-good dies, memory, substrates
OUTPUT
Tested processor packages
NVIDIA · Manufacturing announcement · 2025-04-14 ↗
05
THE PROCESS

Boards, servers & racks

Processors become systems through boards, power delivery, firmware, cooling and validation. Integrators make these parts work together.

INPUT
Processors, boards and components
OUTPUT
Validated server or rack systems
NVIDIA · Manufacturing announcement · 2025-04-14 ↗
06
THE PROCESS

Networking, power & cooling

A rack needs a wider environment: network fabrics exchange data, electrical systems supply energy and cooling removes heat.

INPUT
Racks, network design and utilities
OUTPUT
An operable computing facility
NVIDIA · AI factory digital twins · 2025-05-18 ↗
07
THE PROCESS

Cloud & enterprise deployment

Cloud providers and enterprise operators make computing available to users. Scheduling, isolation, storage and support matter alongside processors.

INPUT
Validated infrastructure and software
OUTPUT
Accessible compute services
NVIDIA · Blackwell announcement · 2024-03-18 ↗
08
THE PROCESS

Software & applications

Libraries, runtimes and deployment tools connect hardware to useful work. Developers and researchers supply models, data and domain knowledge.

INPUT
Models, code, data and compute
OUTPUT
Graphics, simulation and AI services
NVIDIA · NIM deployment · 2024-06-02 ↗
RELATIONSHIPS / 2022—2025

Different roles.
Shared outcomes.

A sourced directory, not an exclusive bill of materials. Dates refer to announcements or reporting periods; plans are not completed facilities.